The present invention relates to a technique that can prevent a bang-bang error occurring in a comparator for comparing a target voltage and a stepwise-varying tracking voltage, and to a counter for counting a code according to the result of the comparison.
Before describing a bang-bang error, a calibration circuit of an on die termination (ODT) device will be described.
Semiconductor devices are implemented in integrated circuit (IC) chips such as central processing units (CPUs), memories, and gate arrays, and are incorporated into a variety of electrical products such as personal computers, servers, and workstations. Most semiconductor devices include an input circuit configured to receive signals from the outside world via input pads, and an output circuit configured to provide internal signals to the outside world via output pads.
As the operating speed of electrical products is increasing, a swing width of a signal exchanged between semiconductor devices is being gradually reduced for minimizing a delay time taken for signal transmission. However, the reduction in the swing width of the signal has a great influence on external noise, causing the signal reflectivity to be more critical at an interface terminal due to impedance mismatch. Such impedance mismatch is generally caused by external noise, a variation of a power supply voltage, a change in an operating temperature, a change in a manufacturing process, etc. The impedance mismatch may lead to difficulty in high-speed data transmission and distortion of output data. Therefore, if semiconductor devices receive the distorted output signal through an input terminal, problems such as a setup/hold failure or an error in decision of an input level may frequently arise.
In particular, in order to resolve the above problems, a memory device requiring high-speed performance employs an impedance matching circuit, which is called an ODT device, near an input pad inside an IC chip. In a typical ODT scheme, source termination is performed at a transmitting end by an output circuit, and parallel termination is performed by a termination circuit connected in parallel to a receiving circuit coupled to the input pad.
ZQ calibration refers to a procedure of generating pull-up and pull-down codes that vary with process, voltage and temperature (PVT) conditions. The resistance of the ODT device, e.g., a termination resistance at a DQ pad in a memory device, is calibrated using the codes resulting from the ZQ calibration. The ZQ calibration is so-named because the calibration is performed using a ZQ node that is a node for calibration.
The ZQ calibration in the ODT device will be described below.
FIG. 1 is a block diagram of a calibration circuit for performing ZQ calibration in a conventional ODT device. Throughout the drawings, VDDQ indicates drain voltage and VSSQ indicates source voltage.
Referring to FIG. 1, the conventional ODT device for performing ZQ calibration includes a pull-up calibration resistor circuit 110, a dummy calibration resistor circuit 120, a pull-down calibration resistor circuit 130, a reference voltage generator 102, comparators 102 and 103, and counters 105 and 106. The pull-up calibration resistor circuit 110 includes a plurality of pull-up resistors which are turned on/off in response to a pull-up calibration code PCODE<0:N>. The dummy calibration resistor circuit 120 is implemented with the same structure as the pull-up calibration resistor circuit 110. The pull-down calibration resistor circuit 130 includes a plurality of pull-down resistors which are turned on/off in response to a pull-down calibration code NCODE<0:N>.
The pull-up calibration resistor circuit 110 generates the primary calibration code PCODE<0:N> while it is calibrated with an external resistor 101 connected to a ZQ node. The dummy calibration resistor circuit 120 and the pull-down calibration resistor circuit 130 generate the secondary calibration code NCODE<0:N> using the calibration code PCODE<0:N> which has been generated through the pull-up calibration resistor circuit 110.
Upon operation of the ODT device, the comparator 103 compares a ZQ node voltage with a reference voltage VREF (generally, VDDQ/2) generated from the reference voltage generator 102 and generates up/down signals (UP/DOWN). Herein, the ZQ node voltage is generated by coupling the pull-up calibration resistor circuit 110 to the external resistor 101 (generally, 240Ω) connected to the ZQ pin that is disposed outside the chip of the ZQ node.
The pull-up counter 105 receives the up/down signals to generate the pull-up calibration code PCODE<0:N> represented with a binary code, which turns on/off the resistors connected in parallel in the pull-up calibration resistor circuit 110, thereby calibrating a total resistance of the pull-up calibration resistor circuit 110. The calibrated resistance of the pull-up calibration resistor circuit 110 affects the ZQ node voltage again and the above-described calibration procedure is then repeated. That is, the pull-up calibration resistor circuit 110 is calibrated such that the total resistance of the pull-up calibration resistor circuit 110 is equal to the resistance of the external resistor 101, which is called a pull-up calibration.
The binary code, i.e., the pull-up calibration code PCODE<0:N>, generated during the pull-up calibration is input to the dummy calibration resistor circuit 120 and determines a total resistance of the dummy calibration circuit 120. Consequently, the dummy calibration resistor circuit will have the same resistance as the pull-up calibration resistor circuit. Thereafter, a pull-down calibration is performed in a similar manner to the pull-up calibration. Specifically, a voltage of a node A is made equal to the reference voltage VREF by using the comparator 104 and the pull-down counter 106. That is, the pull-down calibration is performed to make a total resistance of the pull-down calibration resistor circuit 130 equal to a total resistance of the dummy calibration resistor circuit 120.
The binary codes PCODE<0:N> and NCODE<0:N> resulting from the ZQ calibration, i.e., the pull-up and pull-down calibrations, are input to pull-up and pull-down resistors (termination resistors) at input/output pads, which are designed to have the same structure as the pull-up and pull-down calibration resistor circuits in the calibration circuit of FIG. 1, and determine the resistance of the ODT device. In a memory device, resistances of pull-up and pull-down resistors at a DQ pad are determined.
FIG. 2 is a circuit diagram illustrating how termination resistance of an output driver in a semiconductor memory device is determined using the calibration codes PCODE<0:N> and NCODE<0:N> generated from the calibration circuit of FIG. 1.
The output driver for outputting data in the semiconductor memory device includes pre-drivers 210 and 220 provided in up/down circuits, and pull-up and pull-down termination resistor circuits 230 and 240 for outputting data.
Upon operation of the output driver, the pre-drivers 210 and 220 control the pull-up termination resistor circuit 230 and the pull-down resistor circuit 240, respectively. When outputting high-level data, the pull-up termination resistor circuit 230 is turned on so that a data pin DQ goes to a high state. On the other hand, when outputting low-level data, the pull-down termination resistor circuit 240 is turned on so that the data pin DQ goes to a low state. That is, the data pin DQ is pull-up or pull-down terminated to output the high-level data or low-level data.
At this time, the number of resistors in the pull-up and pull-down termination resistor circuits 230 and 240 to be turned on is determined by the pull-up and pull-down calibration codes PCODE<0:N> and NCODE<0:N>. Specifically, whether to turn on the pull-up termination resistor circuit 230 or the pull-down termination resistor circuit 240 is determined by the logic level of the output data, but the turning on and off of the respective resistors in the turned-on termination resistor circuits 230 and 240 is respectively determined by the pull-up calibration code PCODE<0:N> and the pull-down calibration code NCODE<0:N>.
For reference, target resistances of the pull-up and pull-down resistor circuits 230 and 240 are not necessarily equal to resistances (240Ω) of the calibration resistor circuits (110, 120 and 130 in FIG. 1) but may have a resistance of one-half (120Ω) or one-quarter (60Ω) of 240Ω, etc. In FIG. 2, reference symbols DQp_CTRL and DQn_CTRL input to the pre-drivers 210 and 220 denote a set of various control signals.
FIG. 3 illustrates a procedure of equalizing the ZQ node voltage to the reference voltage through the calibration operation of FIG. 1.
Bang-bang error occurring in the generation of the pull-up calibration code PCODE<0:N> is shown in FIG. 3. The bang-bang error is a phenomenon that the ZQ node voltage keeps fluctuating above and below the reference voltage VREF at regular steps during the calibration operation because the ZQ node voltage is not accurately equal to the reference voltage VREF.
FIG. 4 is a circuit diagram illustrating another conventional calibration circuit in which the comparator of FIG. 1 is improved so as to remove the bang-bang error shown in FIG. 3.
While the calibration circuit of FIG. 1 employs the two comparators 103 and 104, the calibration circuit of FIG. 4 employs four comparators 403_1, 403_2, 404_1 and 404_2, and hold logics 407 and 408 added to up/down circuits respectively.
As for a basic pull-up operation, the comparator 403_1 compares the ZQ node voltage with a reference voltage VREF+A, and the comparator 403_2 compares the ZQ node voltage with a reference voltage VREF-A. The case where outputs of the comparators 403_1 and 403_2 differ from each other means that the ZQ node voltage is in the range of VREF-A to VREF+A. In this case, the hold logic 407 generates a hold signal P_HOLD to disable an operation of a counter 405 and hold the pull-up calibration code PCODE<0:N>. When the hold signal P_HOLD is not activated, the counting operation of the counter 405 is performed using one output P_CNT of the two outputs of the comparators 403_1 and 403_2. Likewise, a pull-down operation is performed in the same manner as the pull-up operation, employing signals N_CNT and N_HOLD.
FIG. 5 is a circuit diagram of the hold logics 407 and 408 in the calibration circuit of FIG. 4.
The two hold logics 407 and 408 may be implemented with the same structure. In FIG. 5, reference symbols OUT_A and OUT_B denote the outputs of the two comparators 403_1 and 403_2 or 404_1 and 404_2. When the outputs OUT_A and OUT_B of the comparators have different logic levels, the hold signal HOLD is activated to a high level and thus the counting operation of the counter 405 or 406 is performed using the counting signal CNT having the same logic level as the output OUT_A of the comparator.
FIG. 6 illustrates a procedure of equalizing the ZQ node voltage to the reference voltage through the calibration operation described with reference to FIG. 4. In FIG. 6, it can be observed that the ZQ node voltage is locked to a predetermined level once the ZQ node voltage falls within a target range.
As described above, the comparators more than the originally required comparators are used for preventing the bang-bang error, and the reference voltages more than the originally required reference voltages are used. Since the comparator is implemented with a differential amplifier or the like, it occupies a large area. Further, an area is significantly increased in implementation of logics for regenerating the reference voltages.
In other words, although the related art can prevent the bang-bang error, it leads to a considerable increase in the entire area of the circuit.